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Towards Xilinx bram support

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This commit is contained in:
Clifford Wolf 2015-01-06 15:26:33 +01:00
parent 4a0b3a5423
commit 9474928672
5 changed files with 178 additions and 28 deletions
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2
techlibs/xilinx/tests/bram1.sh
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@ -1,5 +1,7 @@
#!/bin/bash
set -e
use_xsim=false
unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims

2
techlibs/xilinx/tests/bram1_tb.v
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@ -70,7 +70,7 @@ module bram1_tb #(
expected_rd[j] = RD_DATA[j];
end
$display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end
end
end