mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-27 05:26:02 +00:00
Changed a lot of code to the new RTLIL::Wire constructors
This commit is contained in:
parent
d49dec1f86
commit
946ddff9ce
19 changed files with 156 additions and 224 deletions
|
@ -118,18 +118,13 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
|
|||
std::stringstream sstr;
|
||||
sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
|
||||
|
||||
RTLIL::Wire *wire = new RTLIL::Wire;
|
||||
wire->name = sstr.str();
|
||||
wire->width = sig.size();
|
||||
module->wires[wire->name] = wire;
|
||||
|
||||
RTLIL::SigSpec newsig(wire);
|
||||
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
|
||||
|
||||
for (auto &cell_it : module->cells) {
|
||||
RTLIL::Cell *cell = cell_it.second;
|
||||
if (cell->type == "$dff") {
|
||||
RTLIL::SigSpec new_q = cell->get("\\Q");
|
||||
new_q.replace(sig, newsig);
|
||||
new_q.replace(sig, new_sig);
|
||||
cell->set("\\Q", new_q);
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue