mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-18 01:02:19 +00:00
Code Activity

Changed a lot of code to the new RTLIL::Wire constructors

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 20:12:50 +02:00
parent d49dec1f86
commit 946ddff9ce
19 changed files with 156 additions and 224 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/fsm/fsm_extract.cc
View file

@ -296,10 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::Cell *cell = module->cells.at(cellport.first);
RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = new RTLIL::Wire;
unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
unconn_wire->width = unconn_sig.size();
module->wires[unconn_wire->name] = unconn_wire;
RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size());
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
}
}