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Changed a lot of code to the new RTLIL::Wire constructors

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This commit is contained in:
Clifford Wolf 2014-07-26 20:12:50 +02:00
parent d49dec1f86
commit 946ddff9ce
19 changed files with 156 additions and 224 deletions
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5
passes/fsm/fsm_extract.cc
View file

@ -296,10 +296,7 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::Cell *cell = module->cells.at(cellport.first);
RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = new RTLIL::Wire;
unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
unconn_wire->width = unconn_sig.size();
module->wires[unconn_wire->name] = unconn_wire;
RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size());
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
}
}

20
passes/fsm/fsm_map.cc
View file

@ -143,13 +143,11 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// create state register
RTLIL::Wire *state_wire = new RTLIL::Wire;
state_wire->name = fsm_cell->parameters["\\NAME"].decode_string();
while (module->count_id(state_wire->name) > 0)
state_wire->name += "_";
state_wire->width = fsm_data.state_bits;
module->add(state_wire);
std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string();
while (module->count_id(state_wire_name) > 0)
state_wire_name += "_";
RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
@ -209,10 +207,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// generate next_state signal
RTLIL::Wire *next_state_onehot = new RTLIL::Wire;
next_state_onehot->name = NEW_ID;
next_state_onehot->width = fsm_data.state_table.size();
module->add(next_state_onehot);
RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
@ -275,11 +270,6 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
// Generate ctrl_out signal
RTLIL::Wire *ctrl_out_wire = new RTLIL::Wire;
ctrl_out_wire->name = NEW_ID;
ctrl_out_wire->width = fsm_data.num_outputs;
module->add(ctrl_out_wire);
for (int i = 0; i < fsm_data.num_outputs; i++)
{
std::map<RTLIL::Const, std::set<int>> pattern_cache;