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Changed a lot of code to the new RTLIL::Wire constructors
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parent
d49dec1f86
commit
946ddff9ce
19 changed files with 156 additions and 224 deletions
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@ -28,33 +28,31 @@ struct SplitnetsWorker
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void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
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{
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RTLIL::Wire *new_wire = new RTLIL::Wire;
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std::string new_wire_name = wire->name;
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if (format.size() > 0)
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new_wire_name += format.substr(0, 1);
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if (width > 1) {
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new_wire_name += stringf("%d", offset+width-1);
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if (format.size() > 2)
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new_wire_name += format.substr(2, 1);
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else
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new_wire_name += ":";
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}
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new_wire_name += stringf("%d", offset);
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if (format.size() > 1)
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new_wire_name += format.substr(1, 1);
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while (module->count_id(new_wire_name) > 0)
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new_wire_name += "_";
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RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
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new_wire->port_id = wire->port_id;
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new_wire->port_input = wire->port_input;
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new_wire->port_output = wire->port_output;
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new_wire->name = wire->name;
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new_wire->width = width;
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if (format.size() > 0)
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new_wire->name += format.substr(0, 1);
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if (width > 1) {
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new_wire->name += stringf("%d", offset+width-1);
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if (format.size() > 2)
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new_wire->name += format.substr(2, 1);
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else
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new_wire->name += ":";
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}
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new_wire->name += stringf("%d", offset);
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if (format.size() > 1)
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new_wire->name += format.substr(1, 1);
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while (module->count_id(new_wire->name) > 0)
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new_wire->name = new_wire->name + "_";
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module->add(new_wire);
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std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
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splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
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@ -178,10 +176,10 @@ struct SplitnetsPass : public Pass {
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module->rewrite_sigspecs(worker);
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for (auto &it : worker.splitmap) {
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module->wires.erase(it.first->name);
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delete it.first;
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}
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std::set<RTLIL::Wire*> delete_wires;
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for (auto &it : worker.splitmap)
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delete_wires.insert(it.first);
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module->remove(delete_wires);
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module->fixup_ports();
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}
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