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https://github.com/YosysHQ/yosys
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Changed a lot of code to the new RTLIL::Wire constructors
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parent
d49dec1f86
commit
946ddff9ce
19 changed files with 156 additions and 224 deletions
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@ -21,22 +21,6 @@
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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struct DeleteWireWorker
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{
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RTLIL::Module *module;
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std::set<std::string> *delete_wires_p;
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void operator()(RTLIL::SigSpec &sig) {
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std::vector<RTLIL::SigChunk> chunks = sig;
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for (auto &c : chunks)
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if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
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c.wire = module->addWire(NEW_ID, c.width);
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c.offset = 0;
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}
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sig = chunks;
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}
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};
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struct DeletePass : public Pass {
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DeletePass() : Pass("delete", "delete objects in the design") { }
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virtual void help()
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@ -106,14 +90,14 @@ struct DeletePass : public Pass {
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continue;
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}
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std::set<std::string> delete_wires;
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std::set<RTLIL::Wire*> delete_wires;
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std::set<RTLIL::Cell*> delete_cells;
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std::set<std::string> delete_procs;
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std::set<std::string> delete_mems;
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for (auto &it : module->wires)
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if (design->selected(module, it.second))
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delete_wires.insert(it.first);
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delete_wires.insert(it.second);
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for (auto &it : module->memories)
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if (design->selected(module, it.second))
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@ -131,30 +115,21 @@ struct DeletePass : public Pass {
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if (design->selected(module, it.second))
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delete_procs.insert(it.first);
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DeleteWireWorker delete_wire_worker;
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delete_wire_worker.module = module;
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delete_wire_worker.delete_wires_p = &delete_wires;
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module->rewrite_sigspecs(delete_wire_worker);
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for (auto &it : delete_wires) {
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delete module->wires.at(it);
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module->wires.erase(it);
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}
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for (auto &it : delete_mems) {
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delete module->memories.at(it);
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module->memories.erase(it);
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}
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for (auto &it : delete_cells) {
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for (auto &it : delete_cells)
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module->remove(it);
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}
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for (auto &it : delete_procs) {
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delete module->processes.at(it);
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module->processes.erase(it);
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}
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module->remove(delete_wires);
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module->fixup_ports();
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}
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