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Changed a lot of code to the new RTLIL::Wire constructors

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This commit is contained in:
Clifford Wolf 2014-07-26 20:12:50 +02:00
parent d49dec1f86
commit 946ddff9ce
19 changed files with 156 additions and 224 deletions
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5
passes/cmds/add.cc
View file

@ -47,12 +47,9 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
}
else
{
wire = new RTLIL::Wire;
wire->name = name;
wire->width = width;
wire = module->addWire(name, width);
wire->port_input = flag_input;
wire->port_output = flag_output;
module->add(wire);
if (flag_input || flag_output) {
wire->port_id = module->wires.size();

35
passes/cmds/delete.cc
View file

@ -21,22 +21,6 @@
#include "kernel/rtlil.h"
#include "kernel/log.h"
struct DeleteWireWorker
{
RTLIL::Module *module;
std::set<std::string> *delete_wires_p;
void operator()(RTLIL::SigSpec &sig) {
std::vector<RTLIL::SigChunk> chunks = sig;
for (auto &c : chunks)
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0;
}
sig = chunks;
}
};
struct DeletePass : public Pass {
DeletePass() : Pass("delete", "delete objects in the design") { }
virtual void help()
@ -106,14 +90,14 @@ struct DeletePass : public Pass {
continue;
}
std::set<std::string> delete_wires;
std::set<RTLIL::Wire*> delete_wires;
std::set<RTLIL::Cell*> delete_cells;
std::set<std::string> delete_procs;
std::set<std::string> delete_mems;
for (auto &it : module->wires)
if (design->selected(module, it.second))
delete_wires.insert(it.first);
delete_wires.insert(it.second);
for (auto &it : module->memories)
if (design->selected(module, it.second))
@ -131,30 +115,21 @@ struct DeletePass : public Pass {
if (design->selected(module, it.second))
delete_procs.insert(it.first);
DeleteWireWorker delete_wire_worker;
delete_wire_worker.module = module;
delete_wire_worker.delete_wires_p = &delete_wires;
module->rewrite_sigspecs(delete_wire_worker);
for (auto &it : delete_wires) {
delete module->wires.at(it);
module->wires.erase(it);
}
for (auto &it : delete_mems) {
delete module->memories.at(it);
module->memories.erase(it);
}
for (auto &it : delete_cells) {
for (auto &it : delete_cells)
module->remove(it);
}
for (auto &it : delete_procs) {
delete module->processes.at(it);
module->processes.erase(it);
}
module->remove(delete_wires);
module->fixup_ports();
}

5
passes/cmds/scatter.cc
View file

@ -51,10 +51,7 @@ struct ScatterPass : public Pass {
for (auto &c : mod_it.second->cells)
for (auto &p : c.second->connections_)
{
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = NEW_ID;
wire->width = p.second.size();
mod_it.second->add(wire);
RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
if (ct.cell_output(c.second->type, p.first)) {
RTLIL::SigSig sigsig(p.second, wire);

52
passes/cmds/splitnets.cc
View file

@ -28,33 +28,31 @@ struct SplitnetsWorker
void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
{
RTLIL::Wire *new_wire = new RTLIL::Wire;
std::string new_wire_name = wire->name;
if (format.size() > 0)
new_wire_name += format.substr(0, 1);
if (width > 1) {
new_wire_name += stringf("%d", offset+width-1);
if (format.size() > 2)
new_wire_name += format.substr(2, 1);
else
new_wire_name += ":";
}
new_wire_name += stringf("%d", offset);
if (format.size() > 1)
new_wire_name += format.substr(1, 1);
while (module->count_id(new_wire_name) > 0)
new_wire_name += "_";
RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
new_wire->port_id = wire->port_id;
new_wire->port_input = wire->port_input;
new_wire->port_output = wire->port_output;
new_wire->name = wire->name;
new_wire->width = width;
if (format.size() > 0)
new_wire->name += format.substr(0, 1);
if (width > 1) {
new_wire->name += stringf("%d", offset+width-1);
if (format.size() > 2)
new_wire->name += format.substr(2, 1);
else
new_wire->name += ":";
}
new_wire->name += stringf("%d", offset);
if (format.size() > 1)
new_wire->name += format.substr(1, 1);
while (module->count_id(new_wire->name) > 0)
new_wire->name = new_wire->name + "_";
module->add(new_wire);
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
@ -178,10 +176,10 @@ struct SplitnetsPass : public Pass {
module->rewrite_sigspecs(worker);
for (auto &it : worker.splitmap) {
module->wires.erase(it.first->name);
delete it.first;
}
std::set<RTLIL::Wire*> delete_wires;
for (auto &it : worker.splitmap)
delete_wires.insert(it.first);
module->remove(delete_wires);
module->fixup_ports();
}