mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Changed a lot of code to the new RTLIL::Wire constructors

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 20:12:50 +02:00
parent d49dec1f86
commit 946ddff9ce
19 changed files with 156 additions and 224 deletions
Download patch file Download diff file Expand all files Collapse all files

22
passes/abc/blifparse.cc
View file

@ -98,14 +98,12 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
if (!strcmp(cmd, ".inputs") || !strcmp(cmd, ".outputs")) {
char *p;
while ((p = strtok(NULL, " \t\r\n")) != NULL) {
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = stringf("\\%s", p);
RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
wire->port_id = ++port_count;
if (!strcmp(cmd, ".inputs"))
wire->port_input = true;
else
wire->port_output = true;
module->add(wire);
}
continue;
}
@ -115,17 +113,11 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
char *d = strtok(NULL, " \t\r\n");
char *q = strtok(NULL, " \t\r\n");
if (module->wires.count(RTLIL::escape_id(d)) == 0) {
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = RTLIL::escape_id(d);
module->add(wire);
}
if (module->wires.count(RTLIL::escape_id(d)) == 0)
module->addWire(RTLIL::escape_id(d));
if (module->wires.count(RTLIL::escape_id(q)) == 0) {
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = RTLIL::escape_id(q);
module->add(wire);
}
if (module->wires.count(RTLIL::escape_id(q)) == 0)
module->addWire(RTLIL::escape_id(q));
RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
cell->set("\\D", module->wires.at(RTLIL::escape_id(d)));
@ -162,9 +154,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
if (module->wires.count(stringf("\\%s", p)) > 0) {
wire = module->wires.at(stringf("\\%s", p));
} else {
wire = new RTLIL::Wire;
wire->name = stringf("\\%s", p);
module->add(wire);
wire = module->addWire(stringf("\\%s", p));
}
input_sig.append(wire);
}