mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-27 02:45:52 +00:00
Changed a lot of code to the new RTLIL::Wire constructors
This commit is contained in:
parent
d49dec1f86
commit
946ddff9ce
19 changed files with 156 additions and 224 deletions
|
@ -121,14 +121,13 @@ autoidx_stmt:
|
|||
|
||||
wire_stmt:
|
||||
TOK_WIRE {
|
||||
current_wire = new RTLIL::Wire;
|
||||
current_wire = current_module->addWire("$__ilang_frontend_tmp__");
|
||||
current_wire->attributes = attrbuf;
|
||||
attrbuf.clear();
|
||||
} wire_options TOK_ID EOL {
|
||||
if (current_module->wires.count($4) != 0)
|
||||
rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str());
|
||||
current_wire->name = $4;
|
||||
current_module->wires[$4] = current_wire;
|
||||
current_module->rename(current_wire, $4);
|
||||
free($4);
|
||||
};
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue