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Fitting help messages to 80 character width

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Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
This commit is contained in:
KrystalDelusion 2022-08-24 10:28:27 +12:00
parent 029c2785e8
commit 9465b2af95
35 changed files with 198 additions and 184 deletions
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4
techlibs/ice40/synth_ice40.cc
View file

@ -45,8 +45,8 @@ struct SynthIce40Pass : public ScriptPass
log("This command runs synthesis for iCE40 FPGAs.\n");
log("\n");
log(" -device < hx | lp | u >\n");
log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
log(" default: hx\n");
log(" relevant only for '-abc9' flow, optimise timing for the specified\n");
log(" device. default: hx\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module\n");

13
techlibs/intel/synth_intel.cc
View file

@ -39,21 +39,22 @@ struct SynthIntelPass : public ScriptPass {
log(" -family <max10 | cyclone10lp | cycloneiv | cycloneive>\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" MAX10 is the default target if no family argument specified.\n");
log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
log(" For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n");
log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use\n");
log(" cycloneive. For Cyclone V and Cyclone 10 GX, use the synth_intel_alm\n");
log(" backend instead.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
log("\n");
log(" -vqm <file>\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
log(" output file is omitted if this parameter is not specified.\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing\n");
log(" of an output file is omitted if this parameter is not specified.\n");
log(" Note that this backend has not been tested and is likely incompatible\n");
log(" with recent versions of Quartus.\n");
log("\n");
log(" -vpr <file>\n");
log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
log(" compatible with the Quartus flow. Writing of an\n");
log(" write BLIF files for VPR flow experiments. The synthesized BLIF output\n");
log(" file is not compatible with the Quartus flow. Writing of an\n");
log(" output file is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");

13
techlibs/intel_alm/synth_intel_alm.cc
View file

@ -43,21 +43,24 @@ struct SynthIntelALMPass : public ScriptPass {
log(" -family <family>\n");
log(" target one of:\n");
log(" \"cyclonev\" - Cyclone V (default)\n");
log(" \"arriav\" - Arria V (non-GZ)");
log(" \"arriav\" - Arria V (non-GZ)\n");
log(" \"cyclone10gx\" - Cyclone 10GX\n");
log("\n");
log(" -vqm <file>\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
log(" output file is omitted if this parameter is not specified. Implies -quartus.\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing\n");
log(" of an output file is omitted if this parameter is not specified. Implies\n");
log(" -quartus.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis; useful for per-module area statistics\n");
log(" do not flatten design before synthesis; useful for per-module area\n");
log(" statistics\n");
log("\n");
log(" -quartus\n");
log(" output a netlist using Quartus cells instead of MISTRAL_* cells\n");
log("\n");
log(" -dff\n");
log(" pass DFFs to ABC to perform sequential logic optimisations (EXPERIMENTAL)\n");
log(" pass DFFs to ABC to perform sequential logic optimisations\n");
log(" (EXPERIMENTAL)\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");

4
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -48,8 +48,8 @@ struct SynthQuickLogicPass : public ScriptPass {
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -verilog <file>\n");
log(" write the design to the specified verilog file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log(" write the design to the specified verilog file. writing of an output\n");
log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -abc\n");
log(" use old ABC flow, which has generally worse mapping results but is less\n");

4
techlibs/sf2/synth_sf2.cc
View file

@ -45,8 +45,8 @@ struct SynthSf2Pass : public ScriptPass
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -vlog <file>\n");
log(" write the design to the specified Verilog file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log(" write the design to the specified Verilog file. writing of an output\n");
log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. writing of an output file\n");

7
techlibs/xilinx/synth_xilinx.cc
View file

@ -93,7 +93,8 @@ struct SynthXilinxPass : public ScriptPass
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
log("\n");
log(" -nowidelut\n");
log(" do not use MUXF[5-9] resources to implement LUTs larger than native for the target\n");
log(" do not use MUXF[5-9] resources to implement LUTs larger than native for\n");
log(" the target\n");
log("\n");
log(" -nodsp\n");
log(" do not use DSP48*s to implement multipliers and associated logic\n");
@ -109,8 +110,8 @@ struct SynthXilinxPass : public ScriptPass
log(" infer URAM288s for large memories (xcup only)\n");
log("\n");
log(" -widemux <int>\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n");
log(" above this number of inputs (minimum value 2, recommended value >= 5).\n");
log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at\n");
log(" or above this number of inputs (minimum value 2, recommended value >= 5)\n");
log(" default: 0 (no inference)\n");
log("\n");
log(" -run <from_label>:<to_label>\n");