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Fitting help messages to 80 character width
Uses the regex below to search (using vscode):
^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);
Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
This commit is contained in:
KrystalDelusion
parent
029c2785e8
commit
9465b2af95
35 changed files with 198 additions and 184 deletions
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@ -1532,7 +1532,8 @@ struct AbcPass : public Pass {
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log(" NMUX, AOI3, OAI3, AOI4, OAI4.\n");
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log(" (The NOT gate is always added to this list automatically.)\n");
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log("\n");
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log(" The following aliases can be used to reference common sets of gate types:\n");
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log(" The following aliases can be used to reference common sets of gate\n");
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log(" types:\n");
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log(" simple: AND OR XOR MUX\n");
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log(" cmos2: NAND NOR\n");
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log(" cmos3: NAND NOR AOI3 OAI3\n");
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@ -1576,8 +1577,8 @@ struct AbcPass : public Pass {
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log("\n");
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log(" -dress\n");
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log(" run the 'dress' command after all other ABC commands. This aims to\n");
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log(" preserve naming by an equivalence check between the original and post-ABC\n");
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log(" netlists (experimental).\n");
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log(" preserve naming by an equivalence check between the original and\n");
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log(" post-ABC netlists (experimental).\n");
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log("\n");
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log("When no target cell library is specified the Yosys standard cell library is\n");
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log("loaded into ABC before the ABC script is executed.\n");
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@ -93,8 +93,8 @@ struct Abc9Pass : public ScriptPass
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log("\n");
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log(" abc9 [options] [selection]\n");
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log("\n");
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log("This script pass performs a sequence of commands to facilitate the use of the ABC\n");
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log("tool [1] for technology mapping of the current design to a target FPGA\n");
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log("This script pass performs a sequence of commands to facilitate the use of the\n");
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log("ABC tool [1] for technology mapping of the current design to a target FPGA\n");
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log("architecture. Only fully-selected modules are supported.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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@ -303,8 +303,8 @@ struct Abc9ExePass : public Pass {
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log("\n");
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log(" \n");
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log("This pass uses the ABC tool [1] for technology mapping of the top module\n");
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log("(according to the (* top *) attribute or if only one module is currently selected)\n");
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log("to a target FPGA architecture.\n");
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log("(according to the (* top *) attribute or if only one module is currently\n");
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log("selected) to a target FPGA architecture.\n");
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log("\n");
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log(" -exe <command>\n");
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#ifdef ABCEXTERNAL
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@ -1572,14 +1572,14 @@ struct Abc9OpsPass : public Pass {
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log("the `abc9' script pass. Only fully-selected modules are supported.\n");
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log("\n");
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log(" -check\n");
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log(" check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
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log(" (* abc9_carry *) is only given for one input/output port, etc.\n");
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log(" check that the design is valid, e.g. (* abc9_box_id *) values are\n");
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log(" unique, (* abc9_carry *) is only given for one input/output port, etc.\n");
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log("\n");
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log(" -prep_hier\n");
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log(" derive all used (* abc9_box *) or (* abc9_flop *) (if -dff option)\n");
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log(" whitebox modules. with (* abc9_flop *) modules, only those containing\n");
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log(" $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC limitation\n");
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log(" -- will be derived.\n");
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log(" $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC\n");
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log(" limitation -- will be derived.\n");
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log("\n");
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log(" -prep_bypass\n");
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log(" create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for\n");
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@ -1597,33 +1597,35 @@ struct Abc9OpsPass : public Pass {
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log(" -prep_dff_submod\n");
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log(" within (* abc9_flop *) modules, rewrite all edge-sensitive path\n");
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log(" declarations and $setup() timing checks ($specify3 and $specrule cells)\n");
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log(" that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port to\n");
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log(" the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
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log(" that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port\n");
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log(" to the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
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log(" into the flop box.\n");
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log("\n");
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log(" -prep_dff_unmap\n");
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log(" populate the '$abc9_unmap' design with techmap rules for mapping *_$abc9_flop\n");
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log(" cells back into their derived cell types (where the rules created by\n");
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log(" -prep_hier will then map back to the original cell with parameters).\n");
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log(" populate the '$abc9_unmap' design with techmap rules for mapping\n");
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log(" *_$abc9_flop cells back into their derived cell types (where the rules\n");
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log(" created by -prep_hier will then map back to the original cell with\n");
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log(" parameters).\n");
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log("\n");
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log(" -prep_delays\n");
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log(" insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
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log(" certain required times.\n");
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log("\n");
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log(" -break_scc\n");
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log(" for an arbitrarily chosen cell in each unique SCC of each selected module\n");
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log(" (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt all wires\n");
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log(" driven by this cell's outputs with a temporary $__ABC9_SCC_BREAKER cell\n");
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log(" to break the SCC.\n");
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log(" for an arbitrarily chosen cell in each unique SCC of each selected\n");
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log(" module (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt\n");
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log(" all wires driven by this cell's outputs with a temporary\n");
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log(" $__ABC9_SCC_BREAKER cell to break the SCC.\n");
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log("\n");
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log(" -prep_xaiger\n");
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log(" prepare the design for XAIGER output. this includes computing the\n");
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log(" topological ordering of ABC9 boxes, as well as preparing the '$abc9_holes'\n");
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log(" design that contains the logic behaviour of ABC9 whiteboxes.\n");
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log(" topological ordering of ABC9 boxes, as well as preparing the \n");
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log(" '$abc9_holes' design that contains the logic behaviour of ABC9\n");
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log(" whiteboxes.\n");
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log("\n");
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log(" -dff\n");
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log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
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log(" during -prep_{delays,xaiger,box}.\n");
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log(" consider flop cells (those instantiating modules marked with\n");
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log(" (* abc9_flop *)) during -prep_{delays,xaiger,box}.\n");
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log("\n");
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log(" -prep_lut <maxlut>\n");
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log(" pre-compute the lut library by analysing all modules marked with\n");
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@ -1641,8 +1643,8 @@ struct Abc9OpsPass : public Pass {
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log("\n");
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log(" -reintegrate\n");
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log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n");
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log(" by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
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log(" inputs and outputs.\n");
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log(" by first recovering ABC9 boxes, and then stitching in the remaining\n");
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log(" primary inputs and outputs.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -118,34 +118,24 @@ struct DffLegalizePass : public Pass {
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log("- $_DLATCH_[NP][NP][01]_\n");
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log("- $_DLATCHSR_[NP][NP][NP]_\n");
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log("\n");
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log("The following transformations are performed by this pass:");
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log("\n");
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log("- upconversion from a less capable cell to a more capable cell, if the less");
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log(" capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)");
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log("\n");
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log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)");
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log("\n");
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log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)");
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log("\n");
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log("- adding inverters on the control pins (due to unsupported polarity)");
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log("The following transformations are performed by this pass:\n");
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log("\n");
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log("- upconversion from a less capable cell to a more capable cell, if the less\n");
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log(" capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)\n");
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log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)\n");
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log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)\n");
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log("- adding inverters on the control pins (due to unsupported polarity)\n");
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log("- adding inverters on the D and Q pins and inverting the init/reset values\n");
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log(" (due to unsupported init or reset value)");
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log("\n");
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log("- converting sr into adlatch (by tying D to 1 and using E as set input)");
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log("\n");
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log("- emulating unsupported dffsr cell by adff + adff + sr + mux");
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log("\n");
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log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux");
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log("\n");
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log(" (due to unsupported init or reset value)\n");
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log("- converting sr into adlatch (by tying D to 1 and using E as set input)\n");
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log("- emulating unsupported dffsr cell by adff + adff + sr + mux\n");
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log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux\n");
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log("- emulating adff when the (reset, init) value combination is unsupported by\n");
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log(" dff + adff + dlatch + mux");
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log("\n");
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log(" dff + adff + dlatch + mux\n");
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log("- emulating adlatch when the (reset, init) value combination is unsupported by\n");
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log("- dlatch + adlatch + dlatch + mux");
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log("\n");
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log("If the pass is unable to realize a given cell type (eg. adff when only plain dff");
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log("is available), an error is raised.");
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log("- dlatch + adlatch + dlatch + mux\n");
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log("If the pass is unable to realize a given cell type (eg. adff when only plain dff\n");
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log("is available), an error is raised.\n");
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}
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// Table of all supported cell types.
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@ -431,7 +431,7 @@ struct DfflibmapPass : public Pass {
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log("cells, leaving remaining internal cells untouched.\n");
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log("\n");
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log("When called with -info, this command will only print the target cell\n");
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log("list, along with their associated internal cell types, and the arguments");
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log("list, along with their associated internal cell types, and the arguments\n");
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log("that would be passed to the dfflegalize pass. The design will not be\n");
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log("changed.\n");
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log("\n");
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@ -33,8 +33,8 @@ struct DffunmapPass : public Pass {
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log(" dffunmap [options] [selection]\n");
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log("\n");
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log("This pass transforms FF types with clock enable and/or synchronous reset into\n");
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log("their base type (with neither clock enable nor sync reset) by emulating the clock\n");
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log("enable and synchronous reset with multiplexers on the cell input.\n");
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log("their base type (with neither clock enable nor sync reset) by emulating the\n");
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log("clock enable and synchronous reset with multiplexers on the cell input.\n");
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log("\n");
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log(" -ce-only\n");
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log(" unmap only clock enables, leave synchronous resets alone.\n");
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@ -476,7 +476,8 @@ struct SimplemapPass : public Pass {
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log(" $not, $pos, $and, $or, $xor, $xnor\n");
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log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
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log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
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log(" $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
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log(" $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,\n");
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log(" $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -1026,8 +1026,8 @@ struct TechmapPass : public Pass {
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log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
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log("match cells with a type that match the text value of this attribute. Otherwise\n");
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log("the module name will be used to match the cell. Multiple space-separated cell\n");
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log("types can be listed, and wildcards using [] will be expanded (ie. \"$_DFF_[PN]_\"\n");
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log("is the same as \"$_DFF_P_ $_DFF_N_\").\n");
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log("types can be listed, and wildcards using [] will be expanded (ie.\n");
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log("\"$_DFF_[PN]_\" is the same as \"$_DFF_P_ $_DFF_N_\").\n");
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log("\n");
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log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
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log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
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@ -1083,11 +1083,11 @@ struct TechmapPass : public Pass {
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log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
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log("\n");
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log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
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log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
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log(" connected to this port will be consumed. This wire must have the same\n");
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log(" width as the given port, and for every bit that is set to 1 in the value,\n");
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log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
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log(" bits of an init attribute are left as x, it will be removed.\n");
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log(" When this wire is set to a constant value, the init attribute of the\n");
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log(" wire(s) connected to this port will be consumed. This wire must have\n");
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log(" the same width as the given port, and for every bit that is set to 1 in\n");
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log(" the value, the corresponding init attribute bit will be changed to 1'bx.\n");
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log(" If all bits of an init attribute are left as x, it will be removed.\n");
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log("\n");
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log("In addition to this special wires, techmap also supports special parameters in\n");
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log("modules in the map file:\n");
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@ -1108,8 +1108,8 @@ struct TechmapPass : public Pass {
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log("\n");
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log(" _TECHMAP_WIREINIT_<port-name>_\n");
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log(" When a parameter with this name exists, it will be set to the initial\n");
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log(" value of the wire(s) connected to the given port, as specified by the init\n");
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log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
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log(" value of the wire(s) connected to the given port, as specified by the\n");
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log(" init attribute. If the attribute doesn't exist, x will be filled for the\n");
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log(" missing bits. To remove the init attribute bits used, use the\n");
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log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
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log("\n");
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