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Various ast changes for early expression width detection (prep for constfold fixes)

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This commit is contained in:
Clifford Wolf 2013-11-02 13:00:17 +01:00
parent 0b4a64ac6a
commit 943329c1dc
5 changed files with 146 additions and 30 deletions
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32
frontends/ast/ast.cc
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@ -646,12 +646,37 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe
return node;
}
RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
{
std::vector<RTLIL::State> bits = this->bits;
if (width >= 0 && width < int(bits.size()))
bits.resize(width);
if (width >= 0 && width > int(bits.size())) {
RTLIL::State extbit = RTLIL::State::S0;
if (is_signed && !bits.empty())
extbit = bits.back();
while (width > int(bits.size()))
bits.push_back(extbit);
}
return RTLIL::Const(bits);
}
RTLIL::Const AstNode::bitsAsConst(int width)
{
return bitsAsConst(width, is_signed);
}
// create a new AstModule from an AST_MODULE AST node
static AstModule* process_module(AstNode *ast)
{
assert(ast->type == AST_MODULE);
log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
current_module = new AstModule;
current_module->ast = NULL;
current_module->name = ast->str;
current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
current_ast_mod = ast;
AstNode *ast_before_simplify = ast->clone();
@ -661,7 +686,7 @@ static AstModule* process_module(AstNode *ast)
log("--- END OF AST DUMP ---\n");
}
while (ast->simplify(!flag_noopt, false, false, 0)) { }
while (ast->simplify(!flag_noopt, false, false, 0, -1, false)) { }
if (flag_dump_ast2) {
log("Dumping verilog AST after simplification:\n");
@ -687,11 +712,6 @@ static AstModule* process_module(AstNode *ast)
ast->attributes["\\placeholder"] = AstNode::mkconst_int(1, false);
}
current_module = new AstModule;
current_module->ast = NULL;
current_module->name = ast->str;
current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
ignoreThisSignalsInInitial = RTLIL::SigSpec();
for (auto &attr : ast->attributes) {