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Merge pull request #4626 from povik/select-t-at

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select: Add new `t:@<name>` syntax
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Martin Povišer 2024-10-16 10:18:05 +02:00 committed by GitHub
parent 11e94cc97c f9f509bc25
commit 9432e972f7
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GPG key ID: B5690EEEBB952194
2 changed files with 69 additions and 3 deletions
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20
passes/cmds/select.cc
View file

@ -876,9 +876,20 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
sel.selected_members[mod->name].insert(cell->name); sel.selected_members[mod->name].insert(cell->name);
} else } else
if (arg_memb.compare(0, 2, "t:") == 0) { if (arg_memb.compare(0, 2, "t:") == 0) {
for (auto cell : mod->cells()) if (arg_memb.compare(2, 1, "@") == 0) {
if (match_ids(cell->type, arg_memb.substr(2))) std::string set_name = RTLIL::escape_id(arg_memb.substr(3));
sel.selected_members[mod->name].insert(cell->name); if (!design->selection_vars.count(set_name))
log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str());
auto &muster = design->selection_vars[set_name];
for (auto cell : mod->cells())
if (muster.selected_modules.count(cell->type))
sel.selected_members[mod->name].insert(cell->name);
} else {
for (auto cell : mod->cells())
if (match_ids(cell->type, arg_memb.substr(2)))
sel.selected_members[mod->name].insert(cell->name);
}
} else } else
if (arg_memb.compare(0, 2, "p:") == 0) { if (arg_memb.compare(0, 2, "p:") == 0) {
for (auto &it : mod->processes) for (auto &it : mod->processes)
@ -1164,6 +1175,9 @@ struct SelectPass : public Pass {
log(" t:<pattern>\n"); log(" t:<pattern>\n");
log(" all cells with a type matching the given pattern\n"); log(" all cells with a type matching the given pattern\n");
log("\n"); log("\n");
log(" t:@<name>\n");
log(" all cells with a type matching a module in the saved selection <name>\n");
log("\n");
log(" p:<pattern>\n"); log(" p:<pattern>\n");
log(" all processes with a name matching the given pattern\n"); log(" all processes with a name matching the given pattern\n");
log("\n"); log("\n");

52
tests/select/mod-attribute.ys Normal file
View file

@ -0,0 +1,52 @@
read_rtlil <<EOT
module \pdk_not
wire input 1 \A
wire output 2 \Y
cell $_NOT_ \not
connect \A \A
connect \Y \Y
end
end
module \pdk_buf
wire input 1 \A
wire output 2 \Y
cell $_BUF_ \buf
connect \A \A
connect \Y \Y
end
end
module \top
wire input 1 \A
wire output 2 \Y
wire \w
cell \pdk_buf \buf
connect \A \A
connect \Y \w
end
cell \pdk_not \not
connect \A \w
connect \Y \Y
end
end
EOT
cellmatch -lut_attrs *
select -set buffers a:lut=2'b10 %m
select -set inverters a:lut=2'b01 %m
select -assert-count 1 t:@buffers t:pdk_buf %i
select -assert-count 0 t:@buffers t:pdk_not %i
select -assert-count 0 t:@inverters t:pdk_buf %i
select -assert-count 1 t:@inverters t:pdk_not %i