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Add yosys-smtbmc VCD writer support for memories with async writes

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This commit is contained in:
Clifford Wolf 2017-12-14 03:05:20 +01:00
parent 6132e6e72a
commit 9419de3e37
3 changed files with 11 additions and 7 deletions
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12
backends/smt2/smtbmc.py
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@ -594,7 +594,7 @@ def write_vcd_trace(steps_start, steps_stop, index):
mem_trace_data = dict()
for mempath in sorted(smt.hiermems(topmod)):
abits, width, rports, wports = smt.mem_info(topmod, mempath)
abits, width, rports, wports, asyncwr = smt.mem_info(topmod, mempath)
expr_id = list()
expr_list = list()
@ -666,7 +666,8 @@ def write_vcd_trace(steps_start, steps_stop, index):
else:
buf[k] = tdata[i][k]
tdata.append(data[:])
if not asyncwr:
tdata.append(data[:])
for j_data in wdata[i]:
if j_data["A"] != addr:
@ -679,6 +680,9 @@ def write_vcd_trace(steps_start, steps_stop, index):
if M[k] == "1":
data[k] = D[k]
if asyncwr:
tdata.append(data[:])
assert len(tdata) == len(rdata)
netpath = mempath[:]
@ -785,7 +789,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
mems = sorted(smt.hiermems(vlogtb_topmod))
for mempath in mems:
abits, width, rports, wports = smt.mem_info(vlogtb_topmod, mempath)
abits, width, rports, wports, asyncwr = smt.mem_info(vlogtb_topmod, mempath)
addr_expr_list = list()
data_expr_list = list()
@ -888,7 +892,7 @@ def write_constr_trace(steps_start, steps_stop, index):
mems = sorted(smt.hiermems(constr_topmod))
for mempath in mems:
abits, width, rports, wports = smt.mem_info(constr_topmod, mempath)
abits, width, rports, wports, asyncwr = smt.mem_info(constr_topmod, mempath)
addr_expr_list = list()
data_expr_list = list()