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Merge pull request #1603 from whitequark/ice40-ram_style
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
This commit is contained in:
whitequark
GitHub
commit
93ef516d91
12 changed files with 837 additions and 51 deletions
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@ -5,19 +5,20 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in] <= data_in;
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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assign data_out = data_out_r;
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endmodule // sync_ram_sp
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@ -28,18 +29,19 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in_w] <= data_in;
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data_out_r <= memory[address_in_r];
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end
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always @(posedge clk) begin
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if (write_enable)
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memory[address_in_w] <= data_in;
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data_out_r <= memory[address_in_r];
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end
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assign data_out = data_out_r;
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assign data_out = data_out_r;
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endmodule // sync_ram_sdp
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31
tests/arch/common/blockrom.v
Normal file
31
tests/arch/common/blockrom.v
Normal file
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@ -0,0 +1,31 @@
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`default_nettype none
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module sync_rom #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
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(input wire clk,
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input wire [ADDRESS_WIDTH-1:0] address_in,
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output wire [DATA_WIDTH-1:0] data_out);
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localparam WORD = (DATA_WIDTH-1);
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localparam DEPTH = (2**ADDRESS_WIDTH-1);
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reg [WORD:0] data_out_r;
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reg [WORD:0] memory [0:DEPTH];
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integer i,j = 64'hF4B1CA8127865242;
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initial
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for (i = 0; i <= DEPTH; i++) begin
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// In case this ROM will be implemented in fabric: fill the memory with some data
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// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
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// emit any LUTs at all for `memory[i] = i;`, just a latch.
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memory[i] = j * 64'h2545F4914F6CDD1D;
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j = j ^ (j >> 12);
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j = j ^ (j << 25);
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j = j ^ (j >> 27);
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end
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always @(posedge clk) begin
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data_out_r <= memory[address_in];
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end
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assign data_out = data_out_r;
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endmodule // sync_rom
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330
tests/arch/ecp5/memories.ys
Normal file
330
tests/arch/ecp5/memories.ys
Normal file
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@ -0,0 +1,330 @@
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# ================================ RAM ================================
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# RAM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # too inefficient
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select -assert-count 9 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD # any case works
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:PDPW16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BROM but this is a RAM
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BROM but this is a RAM
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
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# RAM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 9 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 4 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 13 -set DATA_WIDTH 2 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # too inefficient
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select -assert-count 5 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD # any case works
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BROM but this is a RAM
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BROM but this is a RAM
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp -nobram; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
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# RAM bits <= 64; Data width <= 4; Address width <= 4: -> DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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## With parameters
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set syn_ramstyle "distributed" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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setattr -set syn_ramstyle "distributed" m:memory
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synth_ecp5 -top sync_ram_sdp -nolutram; cd sync_ram_sdp
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select -assert-count 1 t:$mem # requested LUTRAM but LUTRAM is disabled
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# ================================ ROM ================================
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# ROM bits <= 18K; Data width <= 36; Address width <= 9: -> PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_rom
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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## With parameters
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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write_ilang
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # too inefficient
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:PDPW16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_romstyle "logic" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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setattr -set logic_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:PDPW16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:$mem # requested BRAM but this is a ROM
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set ram_block 1 m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:$mem # requested BRAM but this is a ROM
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set syn_ramstyle "block_rom" m:memory
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synth_ecp5 -top sync_rom -nobram; cd sync_rom
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select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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setattr -set rom_block 1 m:memory
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synth_ecp5 -top sync_rom -nobram; cd sync_rom
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select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
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# ROM bits <= 18K; Data width <= 18; Address width <= 10: -> DP16KD
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 18 sync_rom
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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## With parameters
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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write_ilang
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synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:DP16KD # too inefficient
|
||||
select -assert-min 9 t:LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set syn_romstyle "ebr" m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:DP16KD
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set rom_block 1 m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:DP16KD
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set syn_romstyle "logic" m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
|
||||
select -assert-min 9 t:LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
|
||||
select -assert-min 9 t:LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set syn_ramstyle "block_ram" m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_ecp5 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set syn_ramstyle "block_rom" m:memory
|
||||
synth_ecp5 -top sync_rom -nobram; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
|
||||
setattr -set rom_block 1 m:memory
|
||||
synth_ecp5 -top sync_rom -nobram; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
read_verilog ../common/lutram.v
|
||||
hierarchy -top lutram_1w1r
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd lutram_1w1r
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
select -assert-none t:SB_RAM40_4K %% t:* %D
|
||||
168
tests/arch/ice40/memories.ys
Normal file
168
tests/arch/ice40/memories.ys
Normal file
|
|
@ -0,0 +1,168 @@
|
|||
# ================================ RAM ================================
|
||||
# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
## With parameters
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 0 t:SB_RAM40_4K # too inefficient
|
||||
select -assert-min 1 t:SB_DFFE
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set syn_ramstyle "block_ram" m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set syn_ramstyle "Block_RAM" m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K # any case works
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set syn_ramstyle "registers" m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
|
||||
select -assert-min 1 t:SB_DFFE
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
|
||||
select -assert-min 1 t:SB_DFFE
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set syn_romstyle "ebr" m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:$mem # requested BROM but this is a RAM
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set rom_block 1 m:memory
|
||||
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
|
||||
select -assert-count 1 t:$mem # requested BROM but this is a RAM
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set syn_ramstyle "block_ram" m:memory
|
||||
synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
|
||||
select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
|
||||
|
||||
design -reset; read_verilog ../common/blockram.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
|
||||
select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
|
||||
|
||||
# ================================ ROM ================================
|
||||
# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
## With parameters
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
write_ilang
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:SB_RAM40_4K # too inefficient
|
||||
select -assert-min 1 t:SB_LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set syn_romstyle "ebr" m:memory
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set rom_block 1 m:memory
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:SB_RAM40_4K
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set syn_romstyle "logic" m:memory
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
|
||||
select -assert-min 1 t:SB_LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set logic_block 1 m:memory
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
|
||||
select -assert-min 1 t:SB_LUT4
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set syn_ramstyle "block_ram" m:memory
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set ram_block 1 m:memory
|
||||
synth_ice40 -top sync_rom; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BRAM but this is a ROM
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set syn_romstyle "ebr" m:memory
|
||||
synth_ice40 -top sync_rom -nobram; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
|
||||
|
||||
design -reset; read_verilog ../common/blockrom.v
|
||||
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
||||
setattr -set rom_block 1 m:memory
|
||||
synth_ice40 -top sync_rom -nobram; cd sync_rom
|
||||
select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
|
||||
Loading…
Add table
Add a link
Reference in a new issue