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docs/source/yosys_internals/formats/cell_library.rst
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.. role:: verilog(code)
:language: Verilog
.. todo:: copypaste
.. _chapter:celllib:
Internal cell library
=====================
.. todo:: less academic, also check formatting consistency
Most of the passes in Yosys operate on netlists, i.e. they only care about the
RTLIL::Wire and RTLIL::Cell objects in an RTLIL::Module. This chapter discusses
the cell types used by Yosys to represent a behavioural design internally.