docs: Updating todos

docs/source/yosys_internals/extensions.rst

@@ -3,7 +3,7 @@
 Writing extensions
 ==================
 
-.. todo:: copypaste
+.. todo:: check text is coherent
 
 This chapter contains some bits and pieces of information about programming
 yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack.
@@ -82,11 +82,11 @@ command has been executed can be helpful.  The
 :doc:`/using_yosys/more_scripting/selections` document has more information on
 using these commands.
 
-.. todo:: copypaste
-
 Creating modules from scratch
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+.. todo:: add/expand supporting text
+
 Let's create the following module using the RTLIL API:
 
 .. code:: Verilog

docs/source/yosys_internals/flow/control_and_data.rst

@@ -1,7 +1,7 @@
 Control and data flow
 =====================
 
-.. todo:: copypaste
+.. todo:: less academic
 
 The data- and control-flow of a typical synthesis tool is very similar to the
 data- and control-flow of a typical compiler: different subsystems are called in

docs/source/yosys_internals/flow/overview.rst

@@ -1,7 +1,7 @@
 Flow overview
 =============
 
-.. todo:: copypaste
+.. todo:: less academic
 
 :numref:`Figure %s <fig:Overview_flow>` shows the simplified data flow within
 Yosys. Rectangles in the figure represent program modules and ellipses internal

docs/source/yosys_internals/formats/cell_library.rst

@@ -1,13 +1,13 @@
 .. role:: verilog(code)
 	:language: Verilog
 
-.. todo:: copypaste
-
 .. _chapter:celllib:
 
 Internal cell library
 =====================
 
+.. todo:: less academic, also check formatting consistency
+
 Most of the passes in Yosys operate on netlists, i.e. they only care about the
 RTLIL::Wire and RTLIL::Cell objects in an RTLIL::Module. This chapter discusses
 the cell types used by Yosys to represent a behavioural design internally.

docs/source/yosys_internals/index.rst

@@ -3,7 +3,7 @@
 Yosys internals
 ===============
 
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+.. todo:: less academic
 
 Yosys is an extensible open source hardware synthesis tool. It is aimed at
 designers who are looking for an easily accessible, universal, and

docs/source/yosys_internals/techmap.rst

@@ -1,6 +1,6 @@
 .. _chapter:techmap:
 
-.. todo:: copypaste
+.. todo:: less academic, check text is coherent
 
 Technology mapping 
 ==================
@@ -109,8 +109,6 @@ sensitive information from the Liberty file.
 Techmap by example
 ------------------
 
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-
 As a quick recap, the :cmd:ref:`techmap` command replaces cells in the design
 with implementations given as Verilog code (called "map files"). It can replace
 Yosys' internal cell types (such as ``$or``) as well as user-defined cell types.
@@ -125,6 +123,8 @@ Yosys' internal cell types (such as ``$or``) as well as user-defined cell types.
 Mapping OR3X1
 ~~~~~~~~~~~~~
 
+.. todo:: add/expand supporting text
+
 .. note::
 
     This is a simple example for demonstration only.  Techmap shouldn't be used