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docs: Updating todos

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Krystine Sherwin 2023-09-19 11:21:15 +12:00
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docs/source/using_yosys/more_scripting/opt_passes.rst
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@ -3,7 +3,7 @@
Optimization passes
===================
.. todo:: copypaste
.. todo:: check text context, also check the optimization passes still do what they say
Yosys employs a number of optimizations to generate better and cleaner results.
This chapter outlines these optimizations.

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docs/source/using_yosys/more_scripting/selections.rst
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@ -1,7 +1,7 @@
Selections
----------
.. todo:: copypaste
.. todo:: expand on text
Most Yosys commands make use of the "selection framework" of Yosys. It can be
used to apply commands only to part of the design. For example:

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docs/source/using_yosys/yosys_flows.rst
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@ -4,7 +4,7 @@ Flows, command types, and order
Command order
-------------
.. todo:: copypaste
.. todo:: check text is coherent
Intro to coarse-grain synthesis
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -39,7 +39,7 @@ The extract pass
subcircuit with an instance of the module from the map file.
- In a way the :cmd:ref:`extract` pass is the inverse of the techmap pass.
.. todo:: copypaste
.. todo:: add/expand supporting text
.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
:class: width-helper
@ -121,7 +121,7 @@ Preconditioning: ``macc_xilinx_swap_map.v``
Make sure ``A`` is the smaller port on all multipliers
.. todo:: copypaste
.. todo:: add/expand supporting text
.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
:language: verilog
@ -277,7 +277,7 @@ Unwrap in ``test2``:
Symbolic model checking
-----------------------
.. todo:: copypaste
.. todo:: check text context
.. note::
@ -299,6 +299,8 @@ Checking.
Checking techmap
~~~~~~~~~~~~~~~~
.. todo:: add/expand supporting text
Remember the following example from :doc:`/getting_started/typical_phases`?
.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
@ -351,6 +353,8 @@ slave keeps ``tready`` asserted all the time. (Something a test bench might do.)
Symbolic Model Checking can be used to expose the bug and find a sequence of
values for ``tready`` that yield the incorrect behavior.
.. todo:: add/expand supporting text
.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_master.v
:language: verilog
:caption: ``docs/resources/PRESENTATION_ExOth/axis_master.v``