From 93c4d005ff92baeccffcdb416ab714812d394b17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Mar 2024 15:19:17 +0100 Subject: [PATCH] verilog: Do not set `module_not_derived` on internal cells --- frontends/ast/genrtlil.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index fe67f00c6..8eb7e2679 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -2087,8 +2087,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) check_unique_id(current_module, id, this, "cell"); RTLIL::Cell *cell = current_module->addCell(id, ""); set_src_attr(cell, this); - // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass - cell->set_bool_attribute(ID::module_not_derived); for (auto it = children.begin(); it != children.end(); it++) { AstNode *child = *it; @@ -2151,6 +2149,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } log_abort(); } + + // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass + if (cell->type.isPublic()) + cell->set_bool_attribute(ID::module_not_derived); + for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) input_error("Attribute `%s' with non-constant value.\n", attr.first.c_str());