3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00

Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr

memory_libmap: look for ram_style attributes on surrounding signals
This commit is contained in:
N. Engelhardt 2023-11-06 16:25:38 +01:00 committed by GitHub
commit 93a426cbbf
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
7 changed files with 166 additions and 8 deletions

View file

@ -140,6 +140,7 @@ X(nomem2reg)
X(nomeminit)
X(nosync)
X(nowrshmsk)
X(no_ram)
X(no_rw_check)
X(O)
X(OFFSET)

View file

@ -148,6 +148,9 @@ void Mem::emit() {
for (int j = 0; j < (1 << wr_ports[i].wide_log2); j++)
wr_port_xlat.push_back(i);
for (auto &port : rd_ports) {
for (auto attr: port.attributes)
if (!cell->has_attribute(attr.first))
cell->attributes.insert(attr);
if (port.cell) {
module->remove(port.cell);
port.cell = nullptr;
@ -210,6 +213,9 @@ void Mem::emit() {
cell->setPort(ID::RD_ADDR, rd_addr);
cell->setPort(ID::RD_DATA, rd_data);
for (auto &port : wr_ports) {
for (auto attr: port.attributes)
if (!cell->has_attribute(attr.first))
cell->attributes.insert(attr);
if (port.cell) {
module->remove(port.cell);
port.cell = nullptr;
@ -246,6 +252,9 @@ void Mem::emit() {
cell->setPort(ID::WR_ADDR, wr_addr);
cell->setPort(ID::WR_DATA, wr_data);
for (auto &init : inits) {
for (auto attr: init.attributes)
if (!cell->has_attribute(attr.first))
cell->attributes.insert(attr);
if (init.cell) {
module->remove(init.cell);
init.cell = nullptr;