mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-02 04:27:53 +00:00
Code Activity

add lut tests

Browse source
This commit is contained in:
Miodrag Milanovic 2024-03-01 10:45:15 +01:00
parent 94b6f19cf0
commit 93543bd874
3 changed files with 15 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

9
tests/arch/nanoxplore/logic.ys Normal file
View file

@ -0,0 +1,9 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/nanoxplore/cells_sim.v synth_nanoxplore # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:NX_LUT
select -assert-none t:NX_LUT %% t:* %D