3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 05:00:52 +00:00

Progress in presentation

This commit is contained in:
Clifford Wolf 2014-02-20 23:44:28 +01:00
parent 4e43cb7317
commit 9351e4d3ca
4 changed files with 51 additions and 11 deletions

View file

@ -0,0 +1,10 @@
module DSP48_MACC (a, b, c, y);
input [24:0] a;
input [17:0] b;
input [47:0] c;
output [47:0] y;
assign y = a*b + c;
endmodule