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Add $bmux and $demux cells.

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This commit is contained in:
Marcelina Kościelnicka 2022-01-24 16:02:29 +01:00
parent db33b1e535
commit 93508d58da
25 changed files with 694 additions and 49 deletions
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46
passes/tests/test_cell.cc
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@ -69,6 +69,48 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
cell->setPort(ID::Y, wire);
}
if (cell_type == ID($bmux))
{
int width = 1 + xorshift32(8);
int swidth = 1 + xorshift32(4);
wire = module->addWire(ID::A);
wire->width = width << swidth;
wire->port_input = true;
cell->setPort(ID::A, wire);
wire = module->addWire(ID::S);
wire->width = swidth;
wire->port_input = true;
cell->setPort(ID::S, wire);
wire = module->addWire(ID::Y);
wire->width = width;
wire->port_output = true;
cell->setPort(ID::Y, wire);
}
if (cell_type == ID($demux))
{
int width = 1 + xorshift32(8);
int swidth = 1 + xorshift32(6);
wire = module->addWire(ID::A);
wire->width = width;
wire->port_input = true;
cell->setPort(ID::A, wire);
wire = module->addWire(ID::S);
wire->width = swidth;
wire->port_input = true;
cell->setPort(ID::S, wire);
wire = module->addWire(ID::Y);
wire->width = width << swidth;
wire->port_output = true;
cell->setPort(ID::Y, wire);
}
if (cell_type == ID($fa))
{
int width = 1 + xorshift32(8);
@ -855,8 +897,10 @@ struct TestCellPass : public Pass {
cell_types[ID($logic_and)] = "ABSY";
cell_types[ID($logic_or)] = "ABSY";
cell_types[ID($mux)] = "*";
cell_types[ID($bmux)] = "*";
cell_types[ID($demux)] = "*";
if (edges) {
cell_types[ID($mux)] = "*";
cell_types[ID($pmux)] = "*";
}