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https://github.com/YosysHQ/yosys
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Add $bmux and $demux cells.
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parent
db33b1e535
commit
93508d58da
25 changed files with 694 additions and 49 deletions
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@ -135,8 +135,6 @@ struct ConstEval
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if (cell->hasPort(ID::S)) {
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sig_s = cell->getPort(ID::S);
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if (!eval(sig_s, undef, cell))
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return false;
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}
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if (cell->hasPort(ID::A))
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@ -151,6 +149,9 @@ struct ConstEval
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int count_maybe_set_s_bits = 0;
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int count_set_s_bits = 0;
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if (!eval(sig_s, undef, cell))
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return false;
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for (int i = 0; i < sig_s.size(); i++)
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{
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RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
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@ -198,6 +199,36 @@ struct ConstEval
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else
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set(sig_y, y_values.front());
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}
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else if (cell->type == ID($bmux))
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{
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if (!eval(sig_s, undef, cell))
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return false;
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if (sig_s.is_fully_def()) {
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int sel = sig_s.as_int();
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int width = GetSize(sig_y);
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SigSpec res = sig_a.extract(sel * width, width);
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if (!eval(res, undef, cell))
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return false;
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set(sig_y, res.as_const());
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} else {
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if (!eval(sig_a, undef, cell))
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return false;
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set(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));
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}
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}
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else if (cell->type == ID($demux))
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{
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if (!eval(sig_a, undef, cell))
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return false;
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if (sig_a.is_fully_zero()) {
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set(sig_y, Const(0, GetSize(sig_y)));
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} else {
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if (!eval(sig_s, undef, cell))
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return false;
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set(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));
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}
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}
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else if (cell->type == ID($fa))
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{
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RTLIL::SigSpec sig_c = cell->getPort(ID::C);
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