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RTLIL: factor out RTLIL::Module::addMemory. NFC.

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This commit is contained in:
whitequark 2020-06-03 14:35:27 +00:00
parent ebbbe2156e
commit 9338ff66b9
4 changed files with 16 additions and 14 deletions
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8
passes/techmap/flatten.cc
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@ -79,15 +79,9 @@ struct FlattenWorker
for (auto &it : tpl->memories) {
IdString m_name = it.first;
apply_prefix(cell->name, m_name);
RTLIL::Memory *m = new RTLIL::Memory;
m->name = m_name;
m->width = it.second->width;
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
RTLIL::Memory *m = module->addMemory(m_name, it.second);
if (m->attributes.count(ID::src))
m->add_strpool_attribute(ID::src, extra_src_attrs);
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
}

8
passes/techmap/techmap.cc
View file

@ -174,15 +174,9 @@ struct TechmapWorker
for (auto &it : tpl->memories) {
IdString m_name = it.first;
apply_prefix(cell->name, m_name);
RTLIL::Memory *m = new RTLIL::Memory;
m->name = m_name;
m->width = it.second->width;
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
RTLIL::Memory *m = module->addMemory(m_name, it.second);
if (m->attributes.count(ID::src))
m->add_strpool_attribute(ID::src, extra_src_attrs);
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
}