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Various bug fixes (related to $macc model testing)

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This commit is contained in:
Clifford Wolf 2014-09-06 20:30:46 +02:00
parent 98e6463ca7
commit 9329a76818
4 changed files with 5 additions and 4 deletions
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3
backends/verilog/verilog_backend.cc
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@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (int i = 0; i < wire->width; i++)
if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
goto this_wire_aint_reg;
reg_wires.insert(wire->name);
if (wire->width)
reg_wires.insert(wire->name);
this_wire_aint_reg:;
}
}