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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor

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This commit is contained in:
Eddie Hung 2019-08-28 10:51:39 -07:00
parent 13424352cc
commit 9314a0a42e
1 changed files with 8 additions and 3 deletions
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11
techlibs/xilinx/cells_sim.v
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@ -380,9 +380,10 @@ endmodule
module SRL16E ( module SRL16E (
output Q, output Q,
input A0, A1, A2, A3, CE,
(* clkbuf_sink *) (* clkbuf_sink *)
input CLK, input CLK,
input A0, A1, A2, A3, CE, D input D
); );
parameter [15:0] INIT = 16'h0000; parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0; parameter [0:0] IS_CLK_INVERTED = 1'b0;
@ -401,7 +402,10 @@ endmodule
module SRLC16E ( module SRLC16E (
output Q, output Q,
output Q15, output Q15,
input A0, A1, A2, A3, CE, CLK, D input A0, A1, A2, A3, CE,
(* clkbuf_sink *)
input CLK,
input D
); );
parameter [15:0] INIT = 16'h0000; parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0; parameter [0:0] IS_CLK_INVERTED = 1'b0;
@ -422,9 +426,10 @@ module SRLC32E (
output Q, output Q,
output Q31, output Q31,
input [4:0] A, input [4:0] A,
input CE,
(* clkbuf_sink *) (* clkbuf_sink *)
input CLK, input CLK,
input CE, D input D
); );
parameter [31:0] INIT = 32'h00000000; parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0; parameter [0:0] IS_CLK_INVERTED = 1'b0;