From 61a00b91313118d414502b19d955bd1b679ade99 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Tue, 9 Sep 2025 13:24:48 +0200 Subject: [PATCH] memory_libmap: Fix use of uninitialized value for async read ports The code in memory_libmap expects `clk_en` to be initialized for all `PortVariant`s but the parsing in memlib.cc didn't initialize it for variants of kind `PortKind::Ar` (async read ports). While this fixes the immediate CI failure, it would be best to refactor the code so it becomes obvious if something isn't initialized. --- passes/memory/memlib.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/memory/memlib.cc b/passes/memory/memlib.cc index 8a7adc9ac..fb256e41c 100644 --- a/passes/memory/memlib.cc +++ b/passes/memory/memlib.cc @@ -855,7 +855,9 @@ struct Parser { PortVariant var; var.options = portopts; var.kind = pdef.kind; - if (pdef.kind != PortKind::Ar) { + if (pdef.kind == PortKind::Ar) { + var.clk_en = false; + } else { const ClockDef *cdef = find_single_cap(pdef.clock, cram.options, portopts, "clock"); if (!cdef) log_error("%s:%d: missing clock capability.\n", filename.c_str(), orig_line);