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opt_clean: refactor

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This commit is contained in:
Emil J. Tywoniak 2026-02-24 12:28:41 +01:00
parent 60681ff126
commit 930bd3acc5
2 changed files with 59 additions and 39 deletions
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91
passes/opt/opt_clean/cells_temp.cc
View file

@ -26,6 +26,56 @@
#include "kernel/yosys_common.h"
#include "passes/opt/opt_clean/shared.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
bool is_signed(RTLIL::Cell* cell) {
return cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
}
bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed(cell));
if (a.has_const(State::Sz)) {
RTLIL::SigSpec new_a;
RTLIL::SigSpec new_y;
for (int i = 0; i < GetSize(a); ++i) {
RTLIL::SigBit b = a[i];
if (b == State::Sz)
return false;
new_a.append(b);
new_y.append(y[i]);
}
a = std::move(new_a);
y = std::move(new_y);
}
if (!y.empty())
new_connections.insert(ctx, {y, a});
return true;
}
bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
bool did_something = false;
for (RTLIL::Cell *cell : cells) {
if (verbose) {
if (cell->type == ID($connect))
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
else if (cell->type == ID($input_port))
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
else
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
}
mod->remove(cell);
did_something = true;
}
return did_something;
}
PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
@ -37,27 +87,8 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
for (int i : ctx.item_range(const_module->cells_size())) {
RTLIL::Cell *cell = const_module->cell_at(i);
if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed);
if (a.has_const(State::Sz)) {
RTLIL::SigSpec new_a;
RTLIL::SigSpec new_y;
for (int i = 0; i < GetSize(a); ++i) {
RTLIL::SigBit b = a[i];
if (b == State::Sz)
continue;
new_a.append(b);
new_y.append(y[i]);
}
a = std::move(new_a);
y = std::move(new_y);
}
if (!y.empty())
new_connections.insert(ctx, {y, a});
delcells.insert(ctx, cell);
if (trim_buf(cell, new_connections, ctx))
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
@ -70,26 +101,10 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
}
}
});
bool did_something = false;
for (RTLIL::SigSig &connection : new_connections) {
module->connect(connection);
}
for (RTLIL::Cell *cell : delcells) {
if (verbose) {
if (cell->type == ID($connect))
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
else if (cell->type == ID($input_port))
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
else
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
}
module->remove(cell);
did_something = true;
}
if (did_something)
if (remove(delcells, module, verbose))
module->design->scratchpad_set_bool("opt.did_something", true);
}

7
passes/opt/opt_clean/inits.cc
View file

@ -23,9 +23,11 @@
#include "kernel/celltypes.h"
#include "kernel/ffinit.h"
#include "kernel/threading.h"
#include "kernel/yosys_common.h"
#include "passes/opt/opt_clean/shared.h"
YOSYS_NAMESPACE_BEGIN
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
ShardedVector<std::pair<SigBit, State>> results(actx.subpool);
@ -123,6 +125,9 @@ bool remove_redundant_inits(ShardedVector<RTLIL::Wire*> wires, bool verbose) {
return did_something;
}
PRIVATE_NAMESPACE_END
YOSYS_NAMESPACE_BEGIN
bool rmunused_module_init(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
{
AnalysisContext actx(module, subpool);