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+/cmp2lcu.v to work efficiently for fully/partially constant inputs

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This commit is contained in:
Eddie Hung 2020-01-20 16:42:17 -08:00
parent f68d723cdc
commit 92d70cafec
1 changed files with 31 additions and 3 deletions
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34
tests/techmap/cmp2lcu.ys
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@ -10,15 +10,43 @@ assign leu = a <= b;
assign les = $signed(a) <= $signed(b); assign les = $signed(a) <= $signed(b);
endmodule endmodule
EOT EOT
proc
equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
design -load postopt design -load postopt
select -assert-count 8 t:$lcu select -assert-count 8 t:$lcu r:WIDTH=5 %i
select -assert-none t:$gt t:$ge t:$lt t:$le select -assert-none t:$gt t:$ge t:$lt t:$le
design -load preopt design -load preopt
equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
design -load postopt design -load postopt
select -assert-count 8 t:$lcu select -assert-count 8 t:$lcu r:WIDTH=7 %i
select -assert-none t:$gt t:$ge t:$lt t:$le
design -reset
read_verilog <<EOT
module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]};
wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]};
assign gtu = c > d;
assign gts = $signed(c) > $signed(d);
assign ltu = c < d;
assign lts = $signed(c) < $signed(d);
assign geu = c >= d;
assign ges = $signed(c) >= $signed(d);
assign leu = c <= d;
assign les = $signed(c) <= $signed(d);
endmodule
EOT
design -save gold
equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5
design -load postopt
select -assert-count 8 t:$lcu r:WIDTH=2 %i
select -assert-none t:$gt t:$ge t:$lt t:$le
design -load preopt
equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3
design -load postopt
select -assert-count 8 t:$lcu r:WIDTH=4 %i
select -assert-none t:$gt t:$ge t:$lt t:$le select -assert-none t:$gt t:$ge t:$lt t:$le