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splitnets new options

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Alain Dargelas 2025-02-19 09:43:53 -08:00
parent ba09c6c173
commit 929c817384
3 changed files with 77 additions and 0 deletions
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tests/various/test_splitnets.v Normal file
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module bottom(input clk, input wire [1:0] i, output reg [1:0] q);
reg [1:0] q1;
always @(posedge clk) begin
q1 <= i;
q <= q1;
end
endmodule
module top(input clk, input wire [1:0] i, output reg [1:0] q);
reg [1:0] q1;
bottom u1 (.clk(clk), .i(i), .q(q1));
not u2 (q, q1);
endmodule