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Respect \A_SIGNED for $shift

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This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
This commit is contained in:
Xiretza 2020-07-03 13:13:21 +02:00 • committed by Marcelina Kościelnicka
parent 22765ef0a5
commit 928fd40c2e
7 changed files with 61 additions and 65 deletions
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10
backends/verilog/verilog_backend.cc
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@ -750,21 +750,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(" = ");
if (cell->getParam(ID::B_SIGNED).as_bool())
{
f << stringf("$signed(");
dump_sigspec(f, cell->getPort(ID::B));
f << stringf(")");
dump_cell_expr_port(f, cell, "B", true);
f << stringf(" < 0 ? ");
dump_sigspec(f, cell->getPort(ID::A));
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" << - ");
dump_sigspec(f, cell->getPort(ID::B));
f << stringf(" : ");
dump_sigspec(f, cell->getPort(ID::A));
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" >> ");
dump_sigspec(f, cell->getPort(ID::B));
}
else
{
dump_sigspec(f, cell->getPort(ID::A));
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" >> ");
dump_sigspec(f, cell->getPort(ID::B));
}