From 3df66027e0de11913aac4b29d6b4ab79550bfb28 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Mar 2020 11:51:31 -0700
Subject: [PATCH 1/2] Add dynamic slicing Verilog testcase

---
 tests/simple/dynslice.v | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/simple/dynslice.v

diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v
new file mode 100644
index 000000000..7236ac3a5
--- /dev/null
+++ b/tests/simple/dynslice.v
@@ -0,0 +1,12 @@
+module dynslice (
+    input clk ,
+    input [9:0] ctrl ,
+    input [15:0] din ,
+    input [3:0] sel ,
+    output reg [127:0] dout
+);
+always @(posedge clk)
+begin
+    dout[ctrl*sel+:16] <= din ;
+end
+endmodule

From 5132f4099b0a09b542cdb32c3bcdee24917ca5f1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Mar 2020 11:52:14 -0700
Subject: [PATCH 2/2] ast: simplify to fully populate dynamic slicing case
 transformation

---
 frontends/ast/simplify.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 04c02d893..073b9cbbe 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1727,7 +1727,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		}
 		did_something = true;
 		newNode = new AstNode(AST_CASE, shift_expr);
-		for (int i = 0; i <= source_width-result_width; i++) {
+		for (int i = 0; i < source_width; i++) {
 			int start_bit = children[0]->id2ast->range_right + i;
 			AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true));
 			AstNode *lvalue = children[0]->clone();