mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970

Browse source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-04-30 15:19:04 +02:00
parent 314ff1e4ca
commit 9268cd1613
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
kernel/rtlil.cc
View file

@ -3456,7 +3456,7 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
pack();
other.pack();
if (chunks_.size() != chunks_.size())
if (chunks_.size() != other.chunks_.size())
return false;
updhash();