mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-06 11:20:27 +00:00
Code Activity

Added read-enable to memory model

Browse source
This commit is contained in:
Clifford Wolf 2015-09-25 12:23:11 +02:00
parent ec92c89659
commit 924d9d6e86
17 changed files with 157 additions and 76 deletions
Download patch file Download diff file Expand all files Collapse all files

4
techlibs/ice40/brams.txt
View file

@ -5,7 +5,7 @@ bram $__ICE40_RAM4K_M0
groups 2
ports 1 1
wrmode 0 1
enable 0 16
enable 1 16
transp 0 0
clocks 2 3
clkpol 2 3
@ -22,7 +22,7 @@ bram $__ICE40_RAM4K_M123
groups 2
ports 1 1
wrmode 0 1
enable 0 1
enable 1 1
transp 0 0
clocks 2 3
clkpol 2 3

10
techlibs/ice40/brams_map.v
View file

@ -168,7 +168,7 @@ module \$__ICE40_RAM4K (
endmodule
module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter [0:0] CLKPOL2 = 1;
parameter [0:0] CLKPOL3 = 1;
@ -179,6 +179,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input [7:0] A1ADDR;
output [15:0] A1DATA;
input A1EN;
input [7:0] B1ADDR;
input [15:0] B1DATA;
@ -213,7 +214,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.RADDR(A1ADDR_11),
.RCLK(CLK2),
.RCLKE(1'b1),
.RE(1'b1),
.RE(A1EN),
.WDATA(B1DATA),
.WADDR(B1ADDR_11),
.MASK(~B1EN),
@ -223,7 +224,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
);
endmodule
module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 8;
@ -242,6 +243,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
@ -298,7 +300,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
.RADDR(A1ADDR_11),
.RCLK(CLK2),
.RCLKE(1'b1),
.RE(1'b1),
.RE(A1EN),
.WDATA(B1DATA_16),
.WADDR(B1ADDR_11),
.WCLK(CLK3),