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Added read-enable to memory model

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This commit is contained in:
Clifford Wolf 2015-09-25 12:23:11 +02:00
parent ec92c89659
commit 924d9d6e86
17 changed files with 157 additions and 76 deletions
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8
manual/CHAPTER_CellLib.tex
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@ -220,8 +220,9 @@ cell is created. Having individual cells for read and write ports has the advant
consolidated using resource sharing passes. In some cases this drastically reduces the number of required
ports on the memory cell.
The {\tt \$memrd} cells have a clock input \B{CLK}, an address input \B{ADDR} and a data output
\B{DATA}. They also have the following parameters:
The {\tt \$memrd} cells have a clock input \B{CLK}, an enable input \B{EN}, an
address input \B{ADDR}, and a data output \B{DATA}. They also have the
following parameters:
\begin{itemize}
\item \B{MEMID} \\
@ -322,6 +323,9 @@ The {\tt \$mem} cell has the following ports:
\item \B{RD\_CLK} \\
This input is \B{RD\_PORTS} bits wide, containing all clock signals for the read ports.
\item \B{RD\_EN} \\
This input is \B{RD\_PORTS} bits wide, containing all enable signals for the read ports.
\item \B{RD\_ADDR} \\
This input is \B{RD\_PORTS}*\B{ABITS} bits wide, containing all address signals for the read ports.