mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 04:28:18 +00:00
Copy-paste typo
This commit is contained in:
parent
6f971470f8
commit
9245f0d3f5
|
@ -758,7 +758,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
||||||
}
|
}
|
||||||
|
|
||||||
if (width < GetSize(sig_a)) {
|
if (width < GetSize(sig_a)) {
|
||||||
cover_list("opt.opt_expr.xbit", "$shiftx", "$shift", cell->type.str());
|
cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str());
|
||||||
sig_a.remove(width, GetSize(sig_a)-width);
|
sig_a.remove(width, GetSize(sig_a)-width);
|
||||||
cell->setPort(ID::A, sig_a);
|
cell->setPort(ID::A, sig_a);
|
||||||
cell->setParam(ID(A_WIDTH), width);
|
cell->setParam(ID(A_WIDTH), width);
|
||||||
|
|
Loading…
Reference in a new issue