Remove tech independent synthesis

tests/ice40/add_sub.ys

@@ -1,6 +1,5 @@
 read_verilog add_sub.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

tests/ice40/adffs.ys

@@ -1,12 +1,12 @@
 read_verilog adffs.v
 proc
 async2sync
-synth -flatten -run coarse # technology-independent coarse grained synthesis
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
-select -assert-count 1 t:SB_DFFE
-select -assert-count 4 t:SB_LUT4
-#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D
-write_verilog adffs_synth.v
+select -assert-count 1 t:SB_DFFN
+select -assert-count 2 t:SB_DFFSR
+select -assert-count 7 t:SB_LUT4
+select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D

tests/ice40/dffs.ys

@@ -1,6 +1,7 @@
 read_verilog dffs.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
+proc
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

tests/ice40/div_mod.ys

@@ -1,6 +1,6 @@
 read_verilog div_mod.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

tests/ice40/latches.ys

@@ -1,5 +1,6 @@
 read_verilog latches.v
 synth_ice40
-select -assert-count 5 t:SB_LUT4
-#select -assert-none t:SB_LUT4 %% t:* %D
+cd top
+select -assert-count 4 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
 write_verilog latches_synth.v

tests/ice40/memory.ys

@@ -1,4 +1,5 @@
 read_verilog memory.v
 synth_ice40
+cd top
 select -assert-count 1 t:SB_RAM40_4K
 write_verilog memory_synth.v

tests/ice40/mul.ys

@@ -1,6 +1,5 @@
 read_verilog mul.v
 hierarchy -top top
-#synth -flatten -run coarse # technology-independent coarse grained synthesis
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module

tests/ice40/mux.ys

@@ -1,6 +1,8 @@
 read_verilog mux.v
-synth_ice40
+proc
+flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
 design -load postopt
-select -assert-count 20 t:SB_LUT4
-select -assert-count 1 t:SB_CARRY
+cd top
+select -assert-count 19 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D

tests/ice40/tribuf.ys

@@ -1,7 +1,8 @@
 read_verilog tribuf.v
 hierarchy -top top
-synth -flatten -run coarse # technology-independent coarse grained synthesis
-equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+proc
+flatten
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_