mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-01 12:07:51 +00:00
Code Activity

Remove tech independent synthesis

Browse source
This commit is contained in:
Eddie Hung 2019-08-22 12:30:49 -07:00
parent 388eb3288c
commit 9224b3bc17
9 changed files with 20 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tests/ice40/memory.ys
View file

@ -1,4 +1,5 @@
read_verilog memory.v
synth_ice40
cd top
select -assert-count 1 t:SB_RAM40_4K
write_verilog memory_synth.v