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Remove tech independent synthesis

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This commit is contained in:
Eddie Hung 2019-08-22 12:30:49 -07:00
parent 388eb3288c
commit 9224b3bc17
9 changed files with 20 additions and 16 deletions
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5
tests/ice40/latches.ys
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@ -1,5 +1,6 @@
read_verilog latches.v
synth_ice40
select -assert-count 5 t:SB_LUT4
#select -assert-none t:SB_LUT4 %% t:* %D
cd top
select -assert-count 4 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
write_verilog latches_synth.v