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Remove tech independent synthesis

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This commit is contained in:
Eddie Hung 2019-08-22 12:30:49 -07:00
parent 388eb3288c
commit 9224b3bc17
9 changed files with 20 additions and 16 deletions
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10
tests/ice40/adffs.ys
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@ -1,12 +1,12 @@
read_verilog adffs.v
proc
async2sync
synth -flatten -run coarse # technology-independent coarse grained synthesis
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_DFFE
select -assert-count 4 t:SB_LUT4
#select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D
write_verilog adffs_synth.v
select -assert-count 1 t:SB_DFFN
select -assert-count 2 t:SB_DFFSR
select -assert-count 7 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D