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Remove tech independent synthesis

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This commit is contained in:
Eddie Hung 2019-08-22 12:30:49 -07:00
parent 388eb3288c
commit 9224b3bc17
9 changed files with 20 additions and 16 deletions
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1
tests/ice40/add_sub.ys
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@ -1,6 +1,5 @@
read_verilog add_sub.v
hierarchy -top top
synth -flatten -run coarse # technology-independent coarse grained synthesis
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module