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Implemented indexed part selects

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This commit is contained in:
Clifford Wolf 2013-11-20 13:05:27 +01:00
parent c4c299eb5a
commit 92035fb38e
4 changed files with 19 additions and 3 deletions
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3
README
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@ -291,9 +291,6 @@ Roadmap / Large-scale TODOs
- VlogHammer: http://www.clifford.at/yosys/vloghammer.html
- yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
- Missing Verilog-2005 features to be implemented soon:
- Indexed part selects
- Technology mapping for real-world applications
- Add "mini synth script" feature to techmap pass
- Add const-folding via cell parameters to techmap pass

3
frontends/verilog/lexer.l
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@ -249,6 +249,9 @@ supply1 { return TOK_SUPPLY1; }
"<<<" { return OP_SSHL; }
">>>" { return OP_SSHR; }
"+:" { return TOK_POS_INDEXED; }
"-:" { return TOK_NEG_INDEXED; }
"/*" { BEGIN(COMMENT); }
<COMMENT>. /* ignore comment body */
<COMMENT>\n /* ignore comment body */

11
frontends/verilog/parser.y
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@ -104,6 +104,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR
%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED
%type <ast> wire_type range non_opt_range expr basic_expr concat_list rvalue lvalue lvalue_concat_list
%type <string> opt_label tok_prim_wrapper hierarchical_id
@ -336,6 +337,16 @@ non_opt_range:
$$->children.push_back($2);
$$->children.push_back($4);
} |
'[' expr TOK_POS_INDEXED expr ']' {
$$ = new AstNode(AST_RANGE);
$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
} |
'[' expr TOK_NEG_INDEXED expr ']' {
$$ = new AstNode(AST_RANGE);
$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
} |
'[' expr ']' {
$$ = new AstNode(AST_RANGE);
$$->children.push_back($2);

5
tests/simple/partsel.v Normal file
View file

@ -0,0 +1,5 @@
module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
wire [5:0] offset = idx << 2;
assign slice_up = data[offset +: 4];
assign slice_down = data[offset + 3 -: 4];
endmodule