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Get rid of sigAset

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This commit is contained in:
Eddie Hung 2019-09-04 17:18:49 -07:00
parent 42548d9790
commit 91ef4457b0
1 changed files with 14 additions and 10 deletions
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24
passes/pmgen/xilinx_dsp.pmg
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@ -1,18 +1,21 @@
pattern xilinx_dsp
state <SigBit> clock
state <std::set<SigBit>> sigAset sigBset
state <SigSpec> sigC sigM sigP sigPused
state <std::set<SigBit>> sigBset
state <SigSpec> sigA sigC sigM sigP sigPused
state <IdString> ffMmuxAB postAddAB postAddMuxAB
match dsp
select dsp->type.in(\DSP48E1)
endmatch
code sigAset sigBset
SigSpec A = port(dsp, \A);
A.remove_const();
sigAset = A.to_sigbit_set();
code sigA sigBset
sigA = port(dsp, \A);
int i;
for (i = GetSize(sigA)-1; i > 0; i--)
if (sigA[i] != sigA[i-1])
break;
sigA.remove(i, GetSize(sigA)-i);
SigSpec B = port(dsp, \B);
B.remove_const();
sigBset = B.to_sigbit_set();
@ -34,21 +37,22 @@ endcode
match ffA
if param(dsp, \AREG).as_int() == 0
if !sigAset.empty()
select ffA->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffA, \CLK_POLARITY).as_bool()
filter includes(port(ffA, \Q).to_sigbit_set(), sigAset)
filter GetSize(port(ffA, \Q)) >= GetSize(sigA)
slice offset GetSize(port(ffA, \Q))
filter offset+GetSize(sigA) <= GetSize(port(ffA, \Q)) && port(ffA, \Q).extract(offset, GetSize(sigA)) == sigA
optional
endmatch
code clock
if (ffA) {
clock = port(ffA, \CLK).as_bit();
for (auto b : port(ffA, \Q))
if (b.wire->get_bool_attribute(\keep))
reject;
clock = port(ffA, \CLK).as_bit();
}
endcode