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Improved scope resolution of local regs in Verilog+AST frontend

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This commit is contained in:
Clifford Wolf 2014-08-05 12:15:53 +02:00
parent 0129d41efa
commit 91dd87e60b
4 changed files with 90 additions and 9 deletions
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frontends/verilog/parser.y
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@ -599,12 +599,11 @@ wire_name:
if (node->is_input || node->is_output)
frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
}
ast_stack.back()->children.push_back(node);
} else {
if (node->is_input || node->is_output)
node->port_id = current_function_or_task_port_id++;
current_function_or_task->children.push_back(node);
}
ast_stack.back()->children.push_back(node);
delete $1;
};