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macc: Rename 'ports' to 'terms' throughout codebase

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This commit is contained in:
Martin Povišer 2025-03-18 13:25:10 +01:00
parent 05cd1e2942
commit 91cd382f8b
8 changed files with 121 additions and 121 deletions
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12
passes/tests/test_cell.cc
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@ -189,17 +189,17 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
} else
size_b = 0;
Macc::port_t this_port;
Macc::term_t this_term;
wire_a->width += size_a;
this_port.in_a = RTLIL::SigSpec(wire_a, wire_a->width - size_a, size_a);
this_term.in_a = RTLIL::SigSpec(wire_a, wire_a->width - size_a, size_a);
wire_a->width += size_b;
this_port.in_b = RTLIL::SigSpec(wire_a, wire_a->width - size_b, size_b);
this_term.in_b = RTLIL::SigSpec(wire_a, wire_a->width - size_b, size_b);
this_port.is_signed = xorshift32(2) == 1;
this_port.do_subtract = xorshift32(2) == 1;
macc.ports.push_back(this_port);
this_term.is_signed = xorshift32(2) == 1;
this_term.do_subtract = xorshift32(2) == 1;
macc.terms.push_back(this_term);
}
// Macc::to_cell sets the input ports
macc.to_cell(cell);