mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
This commit is contained in:
parent
2335c59e5b
commit
91a7a74ac4
2 changed files with 9 additions and 11 deletions
|
@ -174,11 +174,12 @@ struct XAigerWriter
|
|||
undriven_bits.insert(bit);
|
||||
unused_bits.insert(bit);
|
||||
|
||||
bool keep = wire->get_bool_attribute(ID::keep);
|
||||
if (wire->port_input || keep)
|
||||
bool scc = wire->attributes.count(ID(abc9_scc));
|
||||
if (wire->port_input || scc)
|
||||
input_bits.insert(bit);
|
||||
|
||||
if (wire->port_output || keep) {
|
||||
bool keep = wire->get_bool_attribute(ID::keep);
|
||||
if (wire->port_output || keep || scc) {
|
||||
if (bit != wirebit)
|
||||
alias_map[wirebit] = bit;
|
||||
output_bits.insert(wirebit);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue