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techmap: wrap builtin $lcu as golden module in PPA tests

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This commit is contained in:
Emil J. Tywoniak 2024-11-29 00:13:21 +01:00
parent a41ef0271c
commit 91844968fd
3 changed files with 8 additions and 15 deletions
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2
tests/techmap/han-carlson.tcl
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@ -1,7 +1,7 @@
yosys -import yosys -import
read_verilog +/choices/han-carlson.v read_verilog +/choices/han-carlson.v
read_verilog lcu_refined.v read_verilog -icells lcu_refined.v
design -save init design -save init
for {set i 1} {$i <= 16} {incr i} { for {set i 1} {$i <= 16} {incr i} {

2
tests/techmap/kogge-stone.tcl
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@ -1,7 +1,7 @@
yosys -import yosys -import
read_verilog +/choices/kogge-stone.v read_verilog +/choices/kogge-stone.v
read_verilog lcu_refined.v read_verilog -icells lcu_refined.v
design -save init design -save init
for {set i 1} {$i <= 16} {incr i} { for {set i 1} {$i <= 16} {incr i} {

19
tests/techmap/lcu_refined.v
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@ -1,20 +1,13 @@
// Copied from techlibs/common/simlib.v
// with this condition removed: (^{P, G, CI} !== 1'bx)
module lcu (P, G, CI, CO); module lcu (P, G, CI, CO);
parameter WIDTH = 2; parameter WIDTH = 2;
input [WIDTH-1:0] P; // Propagate input [WIDTH-1:0] P, G;
input [WIDTH-1:0] G; // Generate input CI;
input CI; // Carry-in
output reg [WIDTH-1:0] CO; // Carry-out output [WIDTH-1:0] CO;
integer i; reg [WIDTH-1:0] p, g;
always @* begin
CO[0] = G[0] || (P[0] && CI); \$lcu #(.WIDTH(WIDTH)) impl (.P(P), .G(G), .CI(CI), .CO(CO));
for (i = 1; i < WIDTH; i = i+1)
CO[i] = G[i] || (P[i] && CO[i-1]);
end
endmodule endmodule