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DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH

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This commit is contained in:
Eddie Hung 2019-08-01 13:20:34 -07:00
parent fc0b5d5ab6
commit 915f4e34bf
2 changed files with 12 additions and 5 deletions
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15
techlibs/common/mul2dsp.v
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@ -52,7 +52,7 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
generate generate
if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1) if (A_SIGNED != B_SIGNED)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
// NB: A_SIGNED == B_SIGNED from here // NB: A_SIGNED == B_SIGNED from here
else if (A_WIDTH < B_WIDTH) else if (A_WIDTH < B_WIDTH)
@ -103,10 +103,17 @@ module \$__mul (A, B, Y);
genvar i; genvar i;
generate generate
if (A_WIDTH <= 1 || B_WIDTH <= 1) if (0) begin end
`ifdef DSP_A_MINWIDTH
else if (A_WIDTH < `DSP_A_MINWIDTH)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
`ifdef DSP_MINWIDTH `endif
else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH) `ifdef DSP_B_MINWIDTH
else if (B_WIDTH < `DSP_B_MINWIDTH)
wire _TECHMAP_FAIL_ = 1;
`endif
`ifdef DSP_Y_MINWIDTH
else if (Y_WIDTH < `DSP_Y_MINWIDTH)
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
`endif `endif
else if (A_WIDTH > `DSP_A_MAXWIDTH) begin else if (A_WIDTH > `DSP_A_MAXWIDTH) begin

2
techlibs/ice40/synth_ice40.cc
View file

@ -266,7 +266,7 @@ struct SynthIce40Pass : public ScriptPass
run("opt_expr"); run("opt_expr");
run("opt_clean"); run("opt_clean");
if (help_mode || dsp) { if (help_mode || dsp) {
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16", "(if -dsp)");
run("opt_expr", " (if -dsp)"); run("opt_expr", " (if -dsp)");
run("wreduce", " (if -dsp)"); run("wreduce", " (if -dsp)");
run("ice40_dsp", " (if -dsp)"); run("ice40_dsp", " (if -dsp)");