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	DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
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					 2 changed files with 12 additions and 5 deletions
				
			
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			@ -52,7 +52,7 @@ module \$mul (A, B, Y);
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	output [Y_WIDTH-1:0] Y;
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	generate
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	if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)
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	if (A_SIGNED != B_SIGNED)
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		wire _TECHMAP_FAIL_ = 1;
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	// NB: A_SIGNED == B_SIGNED from here
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	else if (A_WIDTH < B_WIDTH)
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			@ -103,10 +103,17 @@ module \$__mul (A, B, Y);
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	genvar i;
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	generate
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		if (A_WIDTH <= 1 || B_WIDTH <= 1)
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        if (0) begin end
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`ifdef DSP_A_MINWIDTH
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		else if (A_WIDTH < `DSP_A_MINWIDTH)
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			wire _TECHMAP_FAIL_ = 1;
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`ifdef DSP_MINWIDTH
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		else if (A_WIDTH+B_WIDTH < `DSP_MINWIDTH || Y_WIDTH < `DSP_MINWIDTH)
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`endif
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`ifdef DSP_B_MINWIDTH
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		else if (B_WIDTH < `DSP_B_MINWIDTH)
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			wire _TECHMAP_FAIL_ = 1;
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`endif
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`ifdef DSP_Y_MINWIDTH
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		else if (Y_WIDTH < `DSP_Y_MINWIDTH)
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			wire _TECHMAP_FAIL_ = 1;
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`endif
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		else if (A_WIDTH > `DSP_A_MAXWIDTH) begin
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